The present invention relates generally to methods for the manufacture of semiconductor devices. More specifically, the present invention relates to a method for reducing defects, particularly pattern collapse, in semiconductor devices incurred during the manufacturing process without sacrificing throughput.
Defects are a major limiting factor for production yield and device function, particularly when the device sizes are reduced and wafer sizes are enlarged to 300 mm. The term “defects”, as used herein, relates to defects that may reduce the yield, or cause the loss, of the semiconductor device such as the collapse of the photoresist pattern on the substrate surface; particulates introduced onto the substrate resulting from processing such as lithography, etching, stripping, and chemical mechanical planarization (CMP) residues; particulates either indigenous to or resulting from manufacturing processes; pattern imperfections such as closed or partially open or blocked contacts or vias; line width variations; and defects resulting from poor adhesion of the resist to the substrate surface.
The drive to reduce defects—thereby improving yield—presents new challenges to the manufacturing steps within the production of the semiconductor device, namely, the lithography, etching, stripping, and chemical-mechanical planarization (CMP) processes. The lithography process generally involves coating a substrate with a positive or negative photoresist, exposing the substrate to a radiation source to provide an image, and developing the substrate to form a patterned photoresist layer on the substrate. This patterned layer acts as a mask for subsequent substrate patterning processes such as etching, doping, and/or coating with metals, other semiconductor materials, or insulating materials. The etching process generally involves removing the surface of the substrate that is not protected by the patterned photoresist using a chemical or plasma etchant thereby exposing the underlying surface for further processing. The stripping process generally involves removing the cross-linked, photoresist pattern from the substrate via wet stripping or oxygen plasma ashing. The CMP process generally involves polishing the surface of the substrate to maintain flatness during processing. All of the aforementioned processes typically employ a rinse step to remove any particulate material that is generated from, or is a by-product of, these processes.
Pattern collapse is becoming an emerging problem in the production of semiconductor devices due to the higher aspect ratios in the new generation of devices. The thickness and aspect ratio of the patterned photoresist layer are important parameters for subsequent etch steps after lithography. At the 130 nm node, the aspect ratio for a photoresist layer having a 500 nm thickness may reach the value of 4. This value may be the point where the capillary force of the developer and/or rinse solution may lead to the collapse of the patterned photoresist layer. Besides capillary forces, the pattern collapse problem may be further influenced by other factors such as the mechanical strength of the resist, application of other coatings, i.e., anti-reflective coatings (ARC), and the nozzle type, position, and centrifugal forces during spin-on application of the photoresist layer.
A main contributor for pattern collapse is the capillary force of water during the post-development drying stage, see Tanaka, T., et al., “Mechanism of Resist Pattern Collapsed During Developer Process”, Jpn. J. Appl. Phys., Vol. 32, 1993, pp. 6059–64. Reducing or eliminating the surface tension of the rinse liquid after pattern development may be used to reduce the capillary force that is exerted on the patterned photoresist layer. Two common approaches, to reduce or eliminate the surface tension of the rinse liquid, may be to freeze-dry the patterned photoresist features or employ supercritical fluids to dry the patterned photoresist layer after development. Both of these approaches may require extra manufacturing steps and special equipment that are not commonly used in semiconductor device fabrication.
A more common approach to reduce the surface tension may be to add a surfactant to the rinse liquid. The ability to reduce the surface tension of water at the air and liquid interface is of great importance in a variety of applications because decreased surface tension generally relates to increased wetting of water on the substrate surface. Surface tension reduction in water-based systems is generally achieved through the addition of surfactants. Equilibrium surface tension performance is important when the system is at rest, though the ability to reduce surface tension under dynamic conditions is of great importance in applications where high surface creation rates are used, i.e., spin coating, rolling, spray coating, and the like. Dynamic surface tension provides a measure of the ability of the solution to lower surface tension and provide wetting under high speed application conditions. Further, in certain applications such as during spray application, it is advantageous that the surfactant reduces the surface tension of the formulation in a manner that minimizes the problem of bubble generation and foaming. Foaming and bubble generation may lead to defects Consequently, considerable efforts have been made in the semiconductor industry towards solving the foaming problem.
Japanese patent JP 95142349A describes adding a fluorine-based surfactant such as ammonium perfluoroalkylsulfonate or perfluoroalkyl ethoxylate to the developer solution or rinse liquid.
U.S. Pat. No. 6,152,148 describes adding a surfactant such as a fluorosurfactant and a tetra alkyl quarternary ammonium hydroxide compound to an aqueous solution used to clean semiconductor wafers having a poly(arylene ether) dielectric film coating after CMP.
The article, Domke, W. D et al., “Pattern Collapse in High Aspect Ratio DUV-and 193 nm Resists”, Proc. SPIE-Int. Soc. Opt. Eng. 3999, 313–321, 2000 (“Domke”), describes adding surfactants to the developer solution to reduce the possibility of pattern collapse of acrylic and cycloolefin-maleic anhydride resists. The “surfactant” added to developer solution was the solvent, isopropyl alcohol. According to Domke, the addition of the “surfactant” in the developer solution did not have a consistent effect on pattern collapse.
PCT application WO 02/23598 describes adding the surfactant ammonium lauryl sulfate into the deionized (DI) water rinse and developer and applying them to a patterned photoresist to minimize or eliminate post-development defects.
Japanese Patent Application JP 96008163A describes adding hot water, an organic solvent, and a surfactant to a post-development rinse to prevent pattern collapse. No specific surfactants were mentioned.
PCT application 87/03387 describes protecting photoresist images against distortion or degradation by heat generated during etching and other processes by applying a thermally stabilizing, protective film to the substrate prior to the post-development bake of the image. Materials used for the film includes fluorocarbon surfactants, film forming polymers, chromium sulfate, trichloroacetic acid, chromotropic acid, and salts thereof.
The article, Cheung, C. et al., “A Study of a Single Closed Contact for 0.18 micron Photolithography Process” Proc. SPIE-Int. Soc. Opt. Eng. 3998, 738–741, 2000 (“Cheung”), discloses the use of surfactants such as octyl and nonyl phenol ethoxylates such as TRITON® X-114, X-102, X-45, and X-15, in the rinse solution to eliminate the photoresist residue and single closed contact defects. According to Cheung, the use of surfactant in the rinse solution did not provide much success.
U.S. Pat. No. 5,977,041 describes a post-stripping, aqueous rinse solution that includes water, a water soluble organic acid, and a water soluble surface-active agent. The surface-active agents include oligo(ethylene oxide) compounds having at least one acetylenic alcohol group.
WO 00/03306 describes a stripper composition that comprises an admixture of a solvent and a surfactant wherein the amount of solvent ranges from about 50 to about 99.9 weight percent of the total composition and the amount of surfactant ranges from about 0.1 to about 30 weight percent of the total composition.
U.S. patent application Ser. No.2002/0115022 describes a developer and a rinse solution that each contains an anionic surfactant such as ammonium perfluoralkyl sulfonate or ammonium perfluoralkyl carboxylate. These solutions are applied in a consecutive sequence to reduce pattern collapse.
The article “Collapse Behavior of Single Layer 193 and 157 nm Resists: Use of Surfactants in the Rinse to Realize the Sub 130 nm Nodes:, Hien et al., Advances in Resist Tech. And Processing XIX, Proceedings of SPIE, Vol. 4690 (2002), pp. 254–261 (“Hien”), applying a rinse solution of 0.10% of a fluorosurfactant and water to a substrate after development to reduce pattern collapse. According to Hein, some of the fluorosurfactants used worsened the collapse behavior.
Although surfactants have been commonly used as a post-development rinse solution, these solutions may not be effective in reducing the surface tension under dynamic conditions. Further, these solutions may have the undesirable side effect of foam generation. Because of these issues, the rinse solution using typical surfactants used in the art may not be effective in reducing all of the defects, particularly pattern collapse defects, in the semiconductor device.
All references cited herein are incorporated herein by reference in their entirety.